Many bus schemes have been developed to enable multiple microprecessors to communicate with each other with and also with shared memory and peripherals. Typically, these processors communicate over a single bus. Various popular bus architectures have reached some level of industry popularity, including the Multibus and VMe-bus. The multiple processors, as well as a variety of peripherals, shared memory and transmission nodes for local area networks are all connected to the same bus.
What that means, however, is that only one processor can communicate with shared memory or peripherals on any given bus cycle. When a processor asks for permission to transmit onto the bus, first it must wait intil the bus is free, and after that, while it is using the bus, all other processors must wait their turns. Obviously such a prior art system requires a "traffic cop", known as a bus arbitrator, to be sure that only one processor at a time uses the bus. Otherwise, total confusion would reign. In other words, if a first processor is talking to shared memory, no other processor may talk either to shared memory or to other peripherals or to another processor while the bus is being used by the first processor. Obviously, therefore, as is well known, the bus creates a bottleneck in the overall data processing speed of a multi-processor system.